Lou Scheffer's page


Here is a collection of areas I've been involved with.  The main areas are:

Professional Publications (Biology)

Scheffer, L. K., & Meinertzhagen, I. A. (2019). The Fly Brain Atlas. Annual review of cell and developmental biology, 35.

Kazunori, S., Huang, G., Lu, Z., Toufiq, P., Shan, X. C., Roxanne, A., ... & Omotara, O. (2019). Comparisons between the ON-and OFF-edge motion pathways in the Drosophila brain. eLife, 8.

Scheffer, L. K. (2018). Analysis tools for large connectomes. Frontiers in neural circuits, 12.

Huang, G. B., Scheffer, L. K., & Plaza, S. M. (2018). Fully-automatic synapse prediction and validation on a large data set. Frontiers in neural circuits, 12.

Scheffer, L. K. (2018, July). Insights from Biology: Low Power Circuits in the Fruit Fly. In Proceedings of the International Symposium on Low Power Electronics and Design (p. 54). ACM.

Gornet, Jonathan, and Louis K. Scheffer. “Simulating extracted connectomes.” bioRxiv (2017): 177113.

Takemura, Shin-ya, Yoshinori Aso, Toshihide Hige, Allan Wong, Zhiyuan Lu, C. Shan Xu, Patricia K. Rivlin et al. “A connectome of a learning and memory center in the adult Drosophila brain.” Elife 6 (2017).

Takemura, S. Y., Nern, A., Chklovskii, D. B., Scheffer, L. K., Rubin, G. M., & Meinertzhagen, I. A. (2017). “The comprehensive connectome of a neural substrate for ONmotion detection in Drosophila”. eLife, 6, e24394.

Beier, T., Pape, C., Rahaman, N., Prange, T., Berg, S., Bock, D. D., ... & Koethe, U. (2017). “Multicut brings automated neurite segmentation closer to human performance”. Nature Methods, 14(2), 101-102.

Huang, G. B., Scheffer, L. K., & Plaza, S. M. (2016). “Fully-automatic synapse prediction and validation on a large data set”. arXiv preprint arXiv:1604.03075.

Bharioke, A., Scheffer, L. K., Chklovskii, D. B., & Meinertzhagen, I. A. (2015). Connectome, Drosophila. Encyclopedia of Computational Neuroscience, 793-798.

Takemura, S. Y., Xu, C. S., Lu, Z., Rivlin, P. K., Parag, T., Olbris, D. J., ... & Weaver, C. (2015). “Synaptic circuits and their variations within different columns in the visual system of Drosophila”. Proceedings of the National Academy of Sciences, 112(44), 13711-13716.

Parag, T., Chakraborty, A., Plaza, S., & Scheffer, L. (2015). “A context-aware delayed agglomeration framework for electron microscopy segmentation”. PloS one, 10(5), e0125825.

Zhao, T., Takemura, S. Y., Huang, G. B., Horne, J. A., Katz, W. T., Shinomiya, K., ... & Plaza, S. M. (2015). “Large-scale EM Analysis of the Drosophila Antennal Lobe with Automatically Computed Synapse Point Clouds”. arXiv preprint arXiv:1508.06232.

Atasoy, D., Betley, J. N., Li, W. P., Su, H. H., Sertel, S. M., Scheffer, L. K., ... & Sternson, S. M. (2014). “A genetically specified connectomics approach applied to long-range feeding regulatory circuits”. Nature neuroscience, 17(12), 1830-1839.

Plaza, S. M., Scheffer, L. K., and Chklovskii, D. B. (2014). “Toward large-scale connectome reconstructions”, Current opinion in neurobiology, 25, 201-210.

Scheffer, L. “Lessons from the Neurons Themselves”, Design Automation Conference (ASP-DAC), Singapore, 2014.

Takemura, S. Y., Bharioke, A., Lu, Z., Nern, A., Vitaladevuni, S., Rivlin, P. K., ... and Chklovskii, D. B. (2013). “A visual motion detection circuit suggested by Drosophila connectomics”, Nature, 500(7461), 175-181.

Scheffer, Louis K., Bill Karsh, and Shiv Vitaladevun. ”Automated alignment of imperfect EM images for neural reconstruction.” arXiv preprint arXiv:1304.6034 (2013).

Scheffer, L.K., “Design tools for artificial nervous systems”, ACM Design Automation Conference, San Francisco, CA, 2012, pp. 717–722.

Rivera-Alba, M., Vitaladevuni, S.N., Mischenko, Y., Lu, Z., Takemura, S., Scheffer, L., Meinertzhagen, I.A., Chklovskii, D.B., and de Polavieja, G.G., “Wiring Economy and Volume Exclusion Determine Neuronal Placement in the Drosophila Brain”, Current Biology, 2011

Veeraraghavan, A., Genkin, A.V., Vitaladevuni, S., Scheffer, L., Xu, S., Hess, H., Fetter, R., Cantoni, M., Knott, G., and Chklovskii, D., “Increasing depth resolution of electron microscopy of neural circuits using sparse tomographic reconstruction”, Computer Vision and Pattern Recognition (CVPR), 2010, pp. 1767–1774.

Chklovskii, D., Vitaladevuni, S., and Scheffer, L. “Semi-automated Reconstruction of Neural Circuits using Electron Microscopy”, Current Opinion in Neurobiology, 2010.

Professional Publications (EE)

Blaaw, D., Chopra, K., Srivastava, A., & Scheffer, L.  (2008) Statistical Timing Analysis, From Basic Principles to State of the Art, IEEE Transactions on Computer Aided Design, 27(4), 589-607.

Scheffer, L. “CAD Implications of New Interconnect Technologies”, Design Automation Conference, San Diego, CA, 2007.

Scheffer, L. “Industrial Floorplanning”, chapter 13 of Handbook of Algorithms for Physical Design Automation, by Alpert, C.J., Mehta, D.P. and Sapatnekar, S.S., 2008, Auerbach.

Scheffer, L., Lavagno, L., and Martin, G., eds. The CRC Handbook of Electronic Design Automation, CRC Press, 2006, ISBN 0-8493-3096-3.

Scheffer, L. “Routing”, Chapter 8 of Voume 2, CRC Handbook of Electronic Design Automation. CRC Press, 2006, pp. 8-1 - 8.18.

William Kao, Chi-Yuan Lo, Mark Basel, Raminderpal Singh, Peter Spink, Lou Scheffer, “Parameter Extraction from Layout”, Chapter 22 of CRC Handbook of Design Automation

Scheffer, L. “MAID - Manufacturing Aware IC Design”, Design and Process Integration for MicroElectronic Manufacturing 2005“, pp 97-107

Scheffer, L. “The Count of Monte Carlo”, TAU -2004

Scheffer, L. “Physical CAD Changes to Incorporate Design for Lithography and Manufacturability”, ASP-DAC 2004

Kahng, A. B., Borkar, S., Cohn, J., Domic, A., Groeneveld, P., Scheffer, L., & Schoellkopf, J. P. (2003, June). Nanometer design: place your bets. In Proceedings of the 40th annual Design Automation Conference (pp. 546-547). ACM.

Scheffer, L. “Some conditions under which hierarchical verification is O(N)”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Volume: 22 , Issue: 5 , May 2003, Pages:643 - 646

Scheffer, L. “Methodologies and tools for pipelined on-chip interconnect”, Proceedings of the IEEE International Conference on Computer Design: VLSI in Computers and Processors, Sept 2002. Pages:152 - 157

Scheffer, L. “ A Cadence Perspective on ICCAD”, in 20 years of ICCAD

Scheffer, L., “Explicit Computation of Performance as a Function of Process Variation”, TAU’02, December 2–3, 2002, Monterey, California, USA.

Scheffer, L., “On Beyond Corners”, Cadence Technical Conference, May 2002.

Scheffer, L., “Data Modeling and Convergence Methodology in Integration Ensemble”, Eighth IEEE/DATC Electronic Design Processes Workshop (EDP), Monterey, CA, 2001

Tseng, H., Scheffer, L., and Sechen, C. , “Timing- and crosstalk-driven area routing ”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Volume: 20 Issue: 4 , April 2001 Page(s): 528 -544

Scheffer, L., R&D Viewpoint: “Conquering Physical Design”, VIEWPOINT: February 05, 2001, http://www.electronicnews.com/
enews/Issue/RegisteredIssues/2001/02052001/z8f-1.asp

Scheffer, L., “Deep Signal Integrity Can be Assured”, EE Times, 16 October 2000, pp. 91,132,134.

Scheffer, L., “What is the Appropriate Model for Crosstalk Control?”, 13th Symposium on Integrated Circuits and System Design, Manaus, Brazil, 2000, pp. 315-320.

Scheffer, L. and Nequist, E., “Why Interconnect Prediction Doesn’t Work”, International Workshop on System Level Interconnect Prediction, San Diego, 2000, pp. 139-144.

Tseng, H., Scheffer, L., and Sechen, C. “Timing and Crosstalk Driven Area Routing”, 35th Design Automation Conference, San Francisco, 1998, pp. 378-381.

A. Domic, P. C. McGeer, A. Saldanha, and L. K. Scheffer, “CAD techniques for lower IC power consumption,” Computer Design, Apr. 1997.

Scheffer, L. “A Roadmap of CAD Tool Changes for Sub-Micron Interconnect Problems”, International Symposium on Physical Design, 1997, pp. 104-109.

Scheffer, L. (moderator) “Deep Sub-micron Design - A D&T Roundtable“, IEEE Design and Test of Computers, Summer 1996, Vol 13, Number 2, p. 83

Scheffer, L. “We’re Solving the Wrong Problems”, in Fifth ACM/SIGDA Physical Design Workshop, Washington, D.C., 1996, pp. 89-91.

Scheffer, L. “CAD tools for Microprocessor Design in the Deep Sub-micron Era”, International Symposium on VLSI Technology, Systems, and Applications, Taipei, Taiwan, 1995.

Scheffer, L. “The Convergence of Structured Custom and ASIC Designs”, Custom Integrated Circuits Conference, Santa Clara, California, 1995.

Scheffer, L. “ASICs, CAD, and Emerging Applications”, ASIC’94 IEEE International ASIC Conference and Exhibit, Rochester, NY, 1994.

Scheffer, L., and Soetarman, R., “Hierarchical Analysis of IC Artwork With User-Defined Rules”, IEEE Design and Test, February 1986, pp. 66-74.

Scheffer, L., and Soetarman, R., “Hierarchical Analysis of IC Artwork With User Defined Abstraction Rules”, Design Automation Conference, Las Vegas, Nevada, 1985

Scheffer, L., “The Use of Strict Hierarchy for Verification of Integrated Circuits”, Ph.D. Thesis, Stanford, 1984

Tucker, M., and Scheffer, L., “A Constrained Design Methodology for VLSI,” VLSI Design, May/June 1982, pp. 60-65.

Scheffer, L., “A Methodology for Improved Verification of VLSI Designs without Loss of Area”, Second Caltech Conference on Very Large Scale Integration (Seitz, ed.), January 1981, pp. 299-309.

Scheffer, L., Apte, R., and Dowell, D., “Design and Simulation of VLSI Circuits,” Hewlett-Packard Journal, June 1981, pp. 12-18.

Scheffer, L., and Apte, R., “LSI Design Verification Using Topology Extraction”, Proc. 12th Asilomar Conference on Circuits, Systems, and Computers, November 1978, pp. 149-153.

Young, T., Scheffer, L., Estreich, D., and Dutton, R., “Macromodelling of IC Structures,” Proc. 1978 Int. Symp. on Circuits and Systems, New York, May 1978, pp. 340-344.

Patents:

US #5,353,243 An Improved Hardware Modelling System and Method of Use

US #5,625,580 Hardware Modelling System and Method of Use

US #6,529,913 Database for electronic design automation applications

US #6,543,041 Method and apparatus for reducing signal integrity and reliability problems in ICS through netlist changes during placement

US #7,024,638 Method for creating patterns for producing integrated circuits

US #7.082,588 Method and apparatus for designing integrated circuit layouts

US #7,207,024 Automatic insertion of clocked elements into an electronic design to improve system performance

US #7,231,628 Method and system for context-specific mask inspection

US #7,249,342 Method and system for context-specific mask writing

US #7,254,798 Method and apparatus for designing integrated circuit layouts

US #7,302,672 Method and system for context-specific mask writing

US #7,395,516 Manufacturing aware design and design aware manufacturing

US #7,474,999 Method for accounting for process variation in the design of integrated circuits

US #7,533,359 Method and system for chip design using physically appropriate component models and extraction

US #7,546,562 Physical integrated circuit design with uncertain design conditions

US #7,627,847 Method and system for representing manufacturing and lithography information for IC routing

US #7,712,064 Manufacturing aware design of integrated circuit layouts

US #7,721,237 Method, system, and computer program product for timing closure in electronic designs

US #7,784,016 Method and system for context-specific mask writing

US #7,814,447 Supplant design rules in electronic designs

US #7,827,519 Method, system, and computer program product for preparing multiple layers of semiconductor substrates for electronic designs

US #7,937,674 Method, system, and computer program product for predicting thin film integrity, manufacturability, reliability, and performance in electronic designs

US #7,962,866 Method, system, and computer program product for determining three-dimensional feature characteristics in electronic designs

US #8,020,135 Manufacturing aware design and design aware manufacturing of an integrated circuit

US #8,103,982 System and method for statistical design rule checking

US #8,103,986 Method and system for representing manufacturing and lithography information for IC routing

US #8,117,566 Method and system for representing manufacturing and lithography information for IC routing

US #8,122,392 Robust design using manufacturability models

US #8,136,056 Method and system for incorporation of patterns and design rule checking

US #8,201,128 Method and apparatus for approximating diagonal lines in placement

US #8,302,061 Aware manufacturing of an integrated circuit

US #8,407,627 Method and system for context-specific mask inspection

US #8,713,484 Aware manufacturing of integrated circuits

US #8,769,453 Method, system, and computer program product for preparing multiple layers of semiconductor substrates for electronic designs

US #8,898,617 Robust design using manufacturability models

Professional Positions and Service

Conference duties: General chair for SLIP, TAU, ISPD, and ICCAD; Technical Chair for ICCAD, SLIP, TAU and ISPD; Technical Program Committee Member for ICCAD, DAC, ISPD, SLIP, and TAU; Publication chair for ISPD; Tutorial Chair for ICCAD; Steering Committee for SLIP. Publicity chair for CANDE. Best paper Committee for DAC, ICCAD, and ISPD. Tutorial presenter, session chair and panelist for many of these conferences. Abbreviations are DAC (Design Automation Conference), ISPD (International Symposium on Physical Design), SLIP (System Level Interconnect Prediction), TAU (Timing Conference) and ICCAD (International Conference on Computer Aided Design)

Associate editor for IEEE TCAD.

Reviewer for various journals - IEEE TCAD, IEEE TVLSI, IEEE Circuits and Systems, and others.

Member of the Board of Governors for IEEE Circuits and Systems Society.

Member of the IEEE Council on Design Automation (CEDA) technical committee.

Member of the SETI Science and Technology Working Group.

Member of the Allen Telescope Array Technical Review Board.

Selection of Invited talks, panels, and tutorials:

VLSID 2018, “Brain Research, the Internet of Things, and New Engineering Ethics”

DAC 2016, “Learning from Life”

ICCAD 2013, “Networks of Neurons and NMOS”

VLSID 2013, “Brain, Cousin to the Chip”

DAC 2012, “Design Tools for Artificial Nervous Systems”

IWLS 2010, “Computing on a Biological Substrate”

BME 2010, “From Images to Neurons: Problems, Progress, and Possibilities”

SLIP 2010, “Ten Years Ago, Ten Years from Now”

ISPD 2010, “Physical Design of Biological Systems”

Tutorial, ICCAD 2009, “Biological Circuits and Systems”

CANDE 2009, “EE and Neural Biology - Twins Separated at Birth?”

Tutorial, DATE 2006, “Design for Manufacturing in the sub-65nm Era”

Tutorial, ASP-DAC 2006, “Design for Manufacturing in the sub-65nm Era”

Tutorial, DAC 2005, “Design for Manufacturing in the sub-65nm Era”

Tutorial, ASP-DAC 2004 “Physical CAD Changes to Incorporate Design for Lithography and Manufacturability”

Invited talk, PATMOS 2003, “Signal Integrity and Power Supply Network Analysis of Deep SubMicron Chips”

Tutorial, DAC-2003, “Design for Manufacturing in the sub-100nm Era”

Panel, DAC 2003, “Nanometer design: place your bets” DAC 2003: 546-547

Panel, IWLS 2003, “Faults and Uncertainty - Do We Need a Totally New Approach?”

Panel, ISQED 2003, “IC and Package Co-design - Challenge or Dream?”

Panel, GLVLSI 2003, “Design and CAD Issues Under Uncertain or Faulty Behavior”

ACM distinguished lecturer for China, 2002. Talk: “Timing Closure and Signal Integrity”

Invited Talk, Conference “SKA: Defining the Future”, Berkeley, CA 2001; talk “Moore’s Law Over the Next Decade”

Panelist, DAC 01, “Who Has Nanometer Design Under Control?”

Tutorial, ASP-DAC 2001, “Timing Closure Today”

Panelist, SBCCI 2000, “EDA and the Web”

Panelist, DAC 00, “Design Closure: Hope or Hype”

Panelist, ISPD 99, “Layout Driven Synthesis or Synthesis Driven Layout?”

Panelist, DAC 97 “Physical Design and Synthesis: Merge or Die”

Tutorial, ASP-DAC 97

Panelist, DAC 96 “Gearing up for the Technology Explosion”

Panelist, PDW 96

Panelist, Design Supercon, Jan 96

Invited Talk, Taiwan 95 “CAD tools for Microprocessor Design”

Invited Talk, CICC 95, “The Convergence of Structured Custom and ASIC Designs”

Invited Talk, ASIC 94, “ASICs, CAD, and Emerging Applications“

Astronomy and SETI

My other interests include astronomy and SETI (Search for Extraterrestial Intelligence).

Member of the SETI Science and Technology Working Group

Member of the Allen Telescope Array Technical Review Board

Scheffer, L. “Investigating nearby exoplanets via interstellar radar”, International Journal of Astrobiology (2013): 1-7.

Scheffer, L. “Large Scale Use of Solar Power may be Visible Across Interstellar Distances”, chapter in “Communication with Extraterrestrial Intelligence”, Doug Vakoch, ed. 2011.

Scheffer, L. “A Scheme for a High Power, Low Cost, Microwave Transmitter for Deep Space Applications”, Radio Science, Vol. 40, RS5012, doi:10.1029/2005RS003243, 2005

Scheffer, L. “Better Lunar Ranges with Fewer Photons - Resolving the Lunar Retro-reflectors”, http://arxiv.org/abs/gr-qc/0504009, 2005

Scheffer, L. “Aliens can watch ‘I Love Lucy’ ” - Contact in Context, 2004

Scheffer, L., “Conventional Forces can Explain the Anomalous Acceleration of Pioneer 10”, Physical Review D, Vol. 67, 084021, 2003.

Ekers, R., Cullers, K., Billingham J., and Scheffer, L., eds. SETI 2020: A Roadmap for the Search for Extraterrestrial Intelligence, , SETI Press, 2002

Scheffer, L., “Machine Intelligence, the Cost of Interstellar Travel, and Fermi’s Paradox”, Quarterly Journal of the Royal Astronomical Society, June 1994.

Wikipedia

I'm a firm believer in contributing to Wikipedia.  A typical article there get more reads in one day than most journal articles get in a year.  Here are some of the articles where I'm one of the most active editors:

Plus many more article on random technical subjects.  And not so seriously

Education

BS, Caltech, 1974, Engineering

MS, Caltech, 1975, Electrical Engineering

Ph.D., Stanford, 1984, Electrical Engineering

Research Experience

2014 - current: Principal Scientist at the Janelia campus of the Howard Hughes Medical Institute. Investigating the structure and function of the nervous system, based on reconstruction of nervous systems from electron microscope images, as inspired by tools already created for IC design.

2019-2014: Fellow at Janelia Farm Campus of the Howard Hughes Medical Institute

2008-2009: Visiting Scientist, Howard Hughes Medical Institute. Investigating if CAD tools built for IC design can help the reverse engineering of nervous systems.

Industrial Experience

1981-2008: Fellow, Cadence Design Systems. Responsible for software architecture of digital IC design tools.

Previous positions within Cadence: Designed and implemented the schematics editor. This product, and its successors, have sold about 15000 copies and is one of the basic components of our PC board solution. Designed hardware and software for a CAE (Computer Aided Engineering) system. Designed the video circuitry (analog and digital) for monochrome and color displays. the hierarchical DRC, and the graphics for a VLSI layout system. Led, and managed, a group of roughly 10 engineers while we designed and implemented a CAD system for custom VLSI design.

1975-1981: Hewlett-Packard. Designed and coded VLSI analysis programs and a schematics editor. Helped design, and did the layout of, a 15000 transistor digital filter chip.

Teaching experience

2008-2009: Gave a series on IC design engineering and computer science for biologists at Janelia Farm campus of the Howard Hughes Medical Institute.

1993: Taught EE-244, “Computer Aided Design of Integrated Circuits” at the University of California at Berkeley. This is a first year grad course that covers (almost) all of physical design automation. Taught primarily from recent research papers.

1991: Taught EE-244, see above.

1990: Taught “Graphic Applications for IC Design” at the Brazilian Microelectronics School, at the invitation of the University of Sao Paulo.

1987: Lecturer at Stanford University. Created and taught a course on Computer Aided Design which covered schematic editors, netlist compilers, logic simulators, timing verifiers, and back annotation from physical design.

1983: Taught portions of a course at UC Berkeley on CAD/CAE tools. I covered graphics hardware (displays, tablets, mice, etc.) and the tools using graphics, such as schematic and layout editors.

1981: Created and taught a grad level course in audio electronics at Stanford. Since there are no textbooks in this field, this involved creating the course from scratch, including lectures, class notes, assignments, and demonstrations.

1977: Created and taught an in-house course in structured programming at HP.

1975: Teaching assistant in “Public Speaking for Engineers” at Caltech.

1974: Taught a basic electronics lab.

1974: Graded a course on switching circuitry.

Contact information

Louis K. Scheffer
19741 Smith Circle
Ashburn, VA 20147
(571) 918-0806 (home)
(571) 209-4151 (work)
email: schefferl@janelia.hhmi.org